1. Field of the Invention
The present invention generally relates to data buses for use in transmitting data between computer devices and, in particular, relates to a technique for minimizing signal skew between a data signal and a clock signal received along independent paths using a data bus.
2. Description of Related Art
Data buses are commonly employed for transmitting data, commands, clock signals or other information between computer devices, such as between a computer and its peripheral equipment, or between components within a single computer. To properly receive data transmitted over a data bus, the receiving device must have the capability of determining the synchronization of the data signal. Hence, a data bus typically transmits not only a data signal but a clock or synchronization signal to allow the receiving device to properly receive and decode the transmitted data.
Although a wide variety of techniques have been developed for transmitting a clock signal along with a data signal, a commonly used technique is to employ a pair of parallel paths, one for transmitting the data signal, the other for transmitting a synchronizing clock signal. Typically, a pair of transmission lines or cables are utilized in tandem with the data transmitted over a first cable with the clock signal transmitted over a second cable.
When the data signal and the clock signal are transmitted over separate paths, the transmission time from transmitter to receiver may vary according to the path. Thus, the clock signal may be delayed or advanced with respect to the data signal, or vice versa. This phenomenon, commonly referred to as skew, may affect the ability of the receiver to properly receive or to decode the data received along the data line.
Parallel path skew is illustrated in FIGS. 1 and 2. FIG. 1 provides a block diagram of a highly simplified serial data bus 10 for receiving a data signal along data line 12 and a synchronizing clock signal along data line 14. The receiver typically includes a D flip-flop for use in sampling the data signal using the synchronizing clock signal to output a binary data signal along output path 16. The clock signal may also be output from the receiver to facilitate further processing of the data. An exemplary data signal (TxData) is shown in FIG. 2 as transmitted data signal 18. The data signal includes blocks or packets of signal pulses defined within bit cells. Data transmitted along path 12 may be encoded subject to conventional data encoding schemes.
Pulse train 20 in FIG. 2 illustrates a synchronization or clock signal(TxClock) transmitted along clock line 14. As can be seen from FIG. 2, the transmitted data signal and the transmitted clock signal are initially synchronized, i.e., rising edges of pulses in clock signal 20 are synchronized with the middle of bit cells in the data packet of transmitted data 18. Pulse sequence 22 (RxData) represents the data signal as it is received by receiver 10, at some arbitrary time later which depends upon the data transmission rate of the serial bus line. Pulse sequence 24 (RxClock) represents the clock signal as it is received by receiver 10. As can be seen from FIG. 2, rising edges of the clock signal are no longer synchronized with the middle of the bit cells. Rather, the rising edges of pulses in clock signal 24 are received well in advance of the middle of bit cells of data packet 22. As a result, with receiver 10 sampling data signal 22 at each rising edge of clock signal 24, receiver 10 may output erroneous data along line 16 because of the shift or skew between the received data and clock signals.
Skew, such as that illustrated in FIG. 2, may arise for a variety of reasons including, for example, a difference in length of data line 12 and clock line 14. Skew may additionally arise due to a mismatch between transmitters used for transmitting the signals onto the data or clock lines or a mismatch between receivers used for receiving the data or clock signals. Skew may also arise due to differences in temperature or voltage of components employed in transmitting or receiving signals over the data bus.
Skew which does not vary significantly as a function of time is commonly referred to as systematic skew. For example, if there is a mismatch in length between the cables of a twisted pair transmission line, that difference in length will produce a constant amount of skew.
Considering skew in more detail, for optimum receiving, the clock edge used by a receiver for sampling data should be aligned with the center of the data bit cell to maximize both the set-up time (the amount of time between a change in the data signal and a change in the clock edge) and the hold time (the amount of time the data is maintained at its previous value following an active clock edge). Setup and hold times are illustrated in FIG. 3 with an exemplary data signal 19 and an exemplary clock signal 21.
The set-up and hold time of the receiving flip-flop of receiver 10 represent only a part of the total set-up and hold times of the receiver. The set-up and hold time of FIG. 3 represents the error margin of the data transmission system and is sufficient to account for most types of random errors (e.g. time jitter, amplitude uncertainty that translates into time jitter, inter-symbol interference that translates into time jitter, duty cycle distortions that translate into time jitter, channel skew, etc.) that may occur in the communication system. Such errors have, in general, equal probability in both time directions.
In the case of FIG. 2, assuming that enough hold time margins exists, a receive error will occur in the case of a burst mode data+clock (synchronous) communication. In such a case the received sequence is 00100011011 instead of 01000110110.
A related skew error occurs if the set-up or hold time becomes too small, as shown in FIG. 4. In this situation the received data may be incorrect, even for a synchronous continuous transmission, because of meta-stability problems resulting from sampling the data signal at the rising and falling edges of the data signal.
A number of techniques has been developed for detecting or minimizing skew between a data signal and a clock signal. In particular, phase-locked-loop (PLL) techniques have been developed for re-synchronizing a clock signal to a data signal. However, PLL-based techniques typically require a substantial lock-in time before the PLL-based system determines the amount of skew and offsets the clock signal to compensate for the skew. Accordingly, such techniques may be ineffective for use in high speed data transmissions employing short bursts of data. In such circumstances, the PLL-based system may not determine the amount of skew until after losing a significant number of bits in an input data packet.
A skew-related problem also occurs at the transmitter. Data transmission systems typically transmit the data and clock signals aligned in quadrature, i.e., the clock edge is in the center of the bit cell. To achieve precise alignment, the transmitter must contain circuits operating with a clock signal having a period equal to one half of the bit cell. For a high speed bus this is a significant technical challenge. As an example, a transmitter operating at 100 Mbps must include circuits operating as fast as 200 MHz.
Another type of distortion, related to skew is clock duty cycle distortion. Clock duty cycle distortion is a type of distortion that occurs on communication lines in which, due to channel imperfections, the "high" clock period becomes shorter (or longer) than the "low" clock period. Such a distortion creates a clock signal with a duty cycle different from 50% so that it is necessary to independently determine the optimum position of the cock rising edge and of the clock falling edge.
Heretofore, no simple, yet effective, techniques have been developed for minimizing skew within high data rate "burst" communication lines. Moreover, no effective techniques have been developed for receiving "burst" communications which relax transmission alignment constraints and allow for compensation of duty cycle distortion.